FIG. 4 is a drawing which shows the configuration of a non-volatile semiconductor memory device of the past. First, the configuration of a non-volatile semiconductor memory device of the past will be described, with reference made to FIG. 4.
As shown in FIG. 4, the non-volatile semiconductor memory device has a control circuit 11, a memory matrix array 13, a row address selection circuit 15, a column address selection circuit 17, a column direction first program circuit 19, a row direction second program circuit 21, a differential sense amplifier circuit 23, an address decoder circuit 25, a comparison reference voltage generation circuit 27, and a data input/output switching circuit 29.
The control circuit 11 is connected to the row address selection circuit 15, the column address selection circuit 17, the column direction first program circuit 19, the row direction second program circuit 21, the differential sense amplifier circuit 23, the comparison reference voltage generation circuit 27, and the data input/output switching circuit 29.
The address decoder circuit 25 is connected to the row address selection circuit 15 and the column address selection circuit 17.
The row address selection circuit 15, the column direction first program circuit 19, and the row direction second program circuit 21 are each connected to the memory matrix array 13.
The data input/output switching circuit 29 is connected to the column address selection circuit 17, and the column address selection circuit 17 is connected to the memory matrix array 13 and the differential sense amplifier circuit 23. The comparison reference voltage generation circuit 27 is connected to the differential sense amplifier circuit 23.
The program operation in a non-volatile semiconductor memory device of the past will be described in terms of FIG. 4. An address signal 33 that is input to the non-volatile semiconductor memory device is input to the address decoder circuit 25, and sent to the row address selection circuit 15 and the column address selection circuit 17.
By means of the address signal 33 that is sent to the row address selection circuit 15 and the column address selection circuit 17, the row address selection circuit 15 and the column address selection circuit 17 select a specific memory of the memory matrix array.
A data 31 that is input to the data input/output switching circuit 29 is sent from the data input/output switching circuit 29 to the column address selection circuit 17 by a control signal from the control circuit 11, the data 31 being input to a specific memory of the memory matrix array that is selected by the row address selection circuit 15 and the column address selection circuit 17.
Finally, by means of a control signal from the control circuit 11, the column direction first program circuit 19 and row direction second program circuit 21 operate, data 31 being programmed into a specific memory of the memory matrix array 13 that is selected by the row address selection circuit 15 and the column address selection circuit 17.
Next, the operation of data readout in a non-volatile semiconductor memory device of the past will be described using FIG. 4. An address signal 33 which is input to the non-volatile semiconductor memory device is input to the address decoder circuit 25, this being sent to the row address selection circuit 15 and the column address selection circuit 17.
By means of the address signal 33 which is sent to the row address selection circuit 15 and the column address selection circuit 17, the row address selection circuit 15 and the column address selection circuit 17 select a specific memory of the memory matrix array 13.
The specific selected memory data of the memory matrix array 13 is sent to the differential sense amplifier circuit 23 via the column address selection circuit 17.
The differential sense amplifier circuit 23 is implemented by a conventional differential amplifier that is used in a general non-volatile semiconductor memory device, a signal voltage that is input to the differential sense amplifier circuit 23 from the comparison reference voltage generation circuit 27 is compared with a memory threshold voltage, which is the memory data that is input from the column address selection circuit 17, the result being sent to the input/output data switching circuit 29.
The signal that is sent to the data input/output switching circuit 29 is output as data 31 by means of a control signal from the control circuit 11.
Next, FIG. 3 will be used to describe the relationship between the memory data threshold voltage and the signal voltage from the comparison reference voltage generation circuit 27. FIG. 3 is a graph which shows the time variation characteristics of the threshold voltage value for memory into which data is programmed.
Both the curve 41 which shows retention of the memory threshold voltage value (data retention) for programming, from the threshold value 45 when the memory is fabricated, in the enhancement direction (that is, with the enhancement direction being the direction in which the Vth of an N-channel memory cell is a positive value of 0 or greater, the condition in the enhancement direction from the threshold value at the time of memory fabrication being defined as the written condition) and the curve 43 which shows the time variations of the memory threshold voltage value for programming, from the threshold value 45 when the memory is fabricated, in the depression direction (that is with the depression direction being the direction in which the Vth of an N-channel memory cell is a negative value of 0 or less, the condition in the depression direction from the threshold value at the time of memory fabrication being defined as the erase condition), approach the threshold voltage value 45 of the memory when fabricated.
In general, the comparison reference voltage value which is the signal voltage from the comparison reference voltage generation circuit 27 is designed to be the same as threshold voltage value 45 of the memory when it is fabricated. The threshold value at the time the memory is fabricated indicates the threshold value Vth (initial Vt) of a memory cell after the completion of the fabrication process and immediately before the first programming of the memory cell.
The differential sense amplifier circuit 23 of FIG. 4 makes a comparison between the threshold voltage value 45 of the memory at the time of fabrication of the memory, which is the same value as the comparison reference voltage value shown in FIG. 3 with the voltage value difference 47 of the memory threshold voltage value 41 of memory programmed in the enhancement direction, or a comparison between the threshold voltage value 45 of the memory at the time of fabrication of the memory, which is the same as the comparison reference voltage value, with the voltage value difference 49 of the memory threshold voltage value 45 of memory programmed in the depression direction, the results thereof being output to the data input/output switching circuit 29 of FIG. 4.
In a different aspect of a rewritable non-volatile semiconductor memory device of the past, and with particular regard to a configuration in the case of high-speed data erasing and data writing, the basic configuration is similar to that which is shown in FIG. 4, in which case the configuration, as illustrated, has a variety of specific signals that are input to the control circuit 11.
That is, a chip enable signal /CE 35, a data output enable signal /OE 36, a chip erase enable signal /EE 37, a program enable signal /PGM 38, and program high-voltage signal VPP 39 are input to the control circuit 11.
Next, FIG. 4 and FIG. 5 will be used to describe the chip erase, the write programming and the readout operations in an electrically rewritable non-volatile semiconductor memory device of the past.
First, using a non-volatile semiconductor memory device of the past such as shown in FIG. 4, the chip erase, write programming, and readout operations in an electrically rewritable non-volatile semiconductor memory device, using the timing which is shown in FIG. 5, will be described.
First, the chip erase will be described. As shown by the chip erase cycle 41 of FIG. 5, in order to erase all of the memories of the memory matrix array 13, the chip enable signal /CE 35 is set to low level, the program high-voltage signal VPP 39 is set to a high-voltage high level, the data output enable signal /OE 36 is set to the high level, the chip erase enable signal /EE 37 is set to the low level, and the program enable signal /PGM 38 is set to the high level. The above-noted settings set the chip erase cycle 41, the memory matrix array 13 being erased during several seconds of the chip erase cycle 41.
The circuit operation will be described next, using FIG. 4.
With regard to signals that are input to the non-volatile semiconductor memory device, when the chip enable signal /CE 35 is changed to the low level, the program high-voltage signal VPP 39 changes to the high-voltage high level, and the chip erase enable signal /EE 37 changes to the low level, the control circuit 11 starts an operation of the chip erase cycle 41 starts, an erase cycle signal being sent to the row address selection circuit 15, the column address selection circuit 17, the column direction first program circuit 19, and the row direction second program circuit 21.
The control circuit 11 maintains the chip erase cycle 41 for several seconds, and several seconds later sends a signal that ends the chip erase cycle 41 to the row address selection circuit 15, the column address selecting circuit 17, the column direction first program circuit 19, and the row direction second program circuit 21.
Next, the writing operation in an electrically rewritable non-volatile semiconductor memory device of the past will be described, using FIG. 5.
In order to write into a memory matrix array 13 such as shown in the write cycle of 42 of FIG. 5, the chip enable signal /CE 35 is set to low level, the program high-voltage signal VPP 39 is set to the high-voltage high level, the data output enable signal /OE 36 is set to the high level, the chip erase enable signal /EE 37 is set to the high level, and the program enable signal /PGM 38 is set to the low level, the address signals A0 through An 33 are input, and the data D0 through Dn 31 are input.
By means of the above-noted settings, the write cycle 42 is set, during the several hundred microseconds of which data D0 through Dn 31 are written into the memory matrix array 13 specified by the address signal A0 through An 33 which are input.
The operation of the circuit under the above-noted conditions will be described using FIG. 4.
With regard to the signals input to the non-volatile semiconductor memory device, when the chip enable signal /CE 35 changes to low, the program high-voltage signal VPP 39 changes to the high-voltage high level, and the program enable signal /PGM 38 changes to the low level, the control circuit 11 starts the write cycle 42, and sends a write cycle signal to the row address selection circuit 15, the column address selection circuit 17, the column direction first program circuit 19, the row direction second program circuit 21, and the data input/output switching circuit 29.
The control circuit 11 maintains the write cycle 42 for several hundred microseconds, after which it sends a signal that ends the write cycle 42 to the row address selection circuit 15, the column address selection circuit 17, the column direction first program circuit 19, the row direction second program circuit 21, and the data input/output switching circuit 29, thereby ending the write cycle 42.
In the earlier background art, however, because of variation with the passage of time of the data threshold voltage value which is stored into a storage memory cell and programmed, it approaches the threshold voltage value at the time the memory was fabricated (initial Vth).
Therefore, there is the problem that the signal voltage values of the memory signal which is input to the differential sense amplifier 23 and the voltage value differences 47 and 49 of the comparison reference voltage value generated by the comparison reference generation circuit 27 become small, the operation of the differential sense amplifier 23 becoming slow, this not only making the readout operation slow, but also increasing the possibility of the generation of a data readout error.
In the latter background art, in order to rewrite data of a memory array 11, it is necessary to execute a write cycle for rewriting the data in memory array 11, after executing a chip erase cycle 41, making it necessary to wait several seconds for the erase cycle before starting the write cycle, this making it difficult to shorten the processing speed.